The semiconductor integrated circuit (IC) industry has experienced rapid growth. Technological advances in IC materials and design have produced generations of ICs where each generation has smaller and more complex circuits than the previous generation. However, these advances have increased the complexity of processing and manufacturing ICs and, for these advances to be realized, similar developments in IC processing and manufacturing are needed. In the mainstream course of IC evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased while geometry size (i.e., the smallest component that can be created using a fabrication process) has decreased. However, this mainstream evolution needs to follow the Moore's rule by a huge investment in facility establishment. Therefore, it has been a study topic that using current semiconductor technology develops more valuable ICs product.
As is well understood in the art, semiconductor devices are typically formed using multiple layers of material, including conductive, semi-conductive, and insulative layers. To provide electrical conductivity between layers in a semiconductor device, a hole or via may be formed through certain layers. The via is then lined with a barrier layer, such as Ti, TiN, or Ti/TiN, and filled with an electrically conductive material, such as a metal, to provide electrical conductivity between the layers.
Currently, a twice-photolithography-twice-etch process is typically used to provide holes or vias with pitches below 115 nm. The cost and processing time is typically double that of a single process for each via layer. Current methods involve long process times, high costs, damage to vias, and concern of via to via overlap. Back-end-of line (BEOL) process issues also need to be minimized. Thus, better methods are needed to define small via pitch dimensions.